Conventional integrated circuit device manufacturing processes for 90 nanometer and smaller devices rely on stress engineering to meet the power and performance requirements of high end devices. In single stress liner processes, stress is only provided to N-Channel Metal Oxide Semiconductor (NMOS) devices. The stress can be provided, for example, by a tensile stress layer that overlies the source, drain and gate of the NMOS device.
In other processes stress is provided to both NMOS devices and P-Channel Metal Oxide Semiconductor (PMOS) devices. One process for providing stress to both NMOS and PMOS devices is the Dual Stress Liner (DSL) fabrication process. In this process, a tensile stress layer is deposited and patterned such that it overlies the source, drain and gate of the NMOS device. A compressive stress layer is then deposited and patterned such that it overlies the source, drain and gate of the PMOS device. This process forms NMOS devices and PMOS devices that are typically referred to as DSL NMOS devices and DSL PMOS devices.
Dual stress liner processes form DSL PMOS devices and DSL NMOS devices having high power and high performance characteristics. More particularly they have high saturation drain current (Idsat) and low leakage current (Ioff). Though the use of conventional DSL NMOS and DSL PMOS devices is sufficient for many applications, integrated circuit designers may require NMOS devices and PMOS devices having different performance levels. Accordingly, there is a need for NMOS devices and PMOS devices that have higher performance levels than traditional non-stressed NMOS and PMOS devices, but not as high as the performance characteristics provided by conventional DSL fabrication processes.